Phase-Locked Loops have been in use on chips for almost 30 years. The basic interface is very straightforward, and so most PLLs offered as IP fit a standard model. They accept a reference clock and generate another clock, frequency multiplied and/or phase-locked to the reference. The differences between PLLs supplied by different vendors essentially come down to three things: the quality of the clocks produced, the useful feature sets of the individual PLLs, and the differences between the vendors themselves.