True Circuits offers a complete line of innovative Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) hard macros in TSMC, GLOBALFOUNDRIES and UMC logic processes spanning nine process generations, from 180nm to 4nm. Our PLLs perform clock generation, deskew, frequency synthesis, jitter filtering and spread-spectrum functions. Our DLLs delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature and are ideal for high-speed DDR interface applications. These PLL and DLL hard macros have excellent jitter performance while operating in the hostile mixed-signal noise environment present in today's ASICs, FPGAs and SoCs. They are extremely versatile, have wide output frequency and multiplication ranges (1-250,000), and are extremely process tolerant. They are available in small sizes and flexible form factors and use only core devices with no extra layer options to avoid extra fabrication costs.

With all of the complexity and demands of your system-on-a-chip project, the last thing you want is to have to worry whether your PLL is going to work properly. Unfortunately, most designers are wary of using PLLs, having learned hard lessons about PLL problems on their earlier chips. Whether composed of digital or analog circuitry, PLLs perform the analog functions of generating and aligning the phases of clock signals. Like analog blocks, they are susceptible to analog issues such as noise, which is commonplace and unavoidable in the hostile mixed-signal environment of today's ICs. Most PLLs available today do not respond well to noise and as a result have very poor jitter performance. They also tend to have narrow ranges of operation (frequency, voltage, etc.) and are generally not very robust to process variations. The jitter performance results commonly published can also be misleading since measuring jitter correctly can be challenging. Jitter results are often obtained in a noise-free environment or by applying the wrong type of noise, which can yield optimistic and misleading jitter results.

True Circuits believes superior analog and mixed-signal circuit technology is developed through dedicated R&D by circuit designers who clearly understand the underlying complexities of real world IC applications. At TCI, circuit R&D is a priority, not a pastime. Over the years, we have developed a fully automated design environment called JSPICE Design Environment^TM that enables our designers to rapidly create and fully characterize our hard macros. Before any macro leaves our hands, it undergoes intensive transistor-level Monte-Carlo SPICE simulations utilizing over 500 current generation processors on our server farm, as well as cloud servers, to fully validate the design. We also design test chips that include our latest PLL, DLL and DDR PHY designs and place them on foundry MPWs. We fully validate the test chips in our silicon lab, using a highly automated parametric lab characterization process that confirms silicon performance.

By selecting PLLs and DLLs developed by True Circuits, you won't have to deal with the typical problems and uncertainties associated with licensing marginal quality IP for your chip designs. TCI PLL and DLL hard macros are based on state-of-the-art technology developed by Dr. John G. Maneatis, world renowned for his innovative work in the area of PLL design. Under his direction, TCI has developed a complete line of leading-edge PLLs and DLLs that are versatile, produce very low jitter, and are highly process tolerant. TCI's entire business model and product line have been specifically designed so customers can license premium quality timing IP quickly and easily with the highest confidence that their chip design will work on the first silicon.