"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading design portfolio and flow, our ASIC customers benefit with exceptional performance and reliability. Combined with our custom chip design expertise, these hard macros enable us to quickly and cost-effectively implement ASIC designs with analog components for high-volume applications."

Prasad Subramaniam
Vice President Design Technology
eSilicon



Given that we maintain state-of-the-art PLL intellectual property, we cannot perform such consulting without risking contamination which will compromise our business model.


23 Jun 25 True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL that Offers Exceptional Performance, Features and Ease of Use

19 Jun 25 True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
Will also showcase other high-performance PLL, DLL and DDR PHY IP and powerful JSPICETM Design Environment (JDETM)

24 Jun 24 True Circuits Introduces the JSPICETM Design Environment (JDETM) at the Design Automation Conference

06 Jul 23 True Circuits Attends 60th Design Automation Conference and Celebrates 25 Years of Timing Excellence!

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