"We selected a PLL from TCI because of the company's PLL expertise and reputation for supplying proven PLL hard macros. The TCI 1.2GHz clock generator PLL is the core component that allows the multi-rate SONET/SDH ports on the ADM-on-a-Chip to operate within the required industry jitter specifications across all supported rates."

Kent Goodin, Vice President, VLSI Engineering, Parama Networks

The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.