"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas

The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.