"We chose TCI because of their expertise in PLLs and the proven nature of their PLL designs. By going with TCI in the future, we feel we can spend more time designing our embedded cores and less time doing test chip integration work."

Ken Reimer
Austin Design Center Manager
ARM



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


14 Jun 17 True Circuits Attends Design Automation Conference

14 Mar 17 True Circuits Showcases State-of-the-art PLLs and 16nm IP

30 May 16 True Circuits Attends Design Automation Conference

14 Mar 16 True Circuits Announces New Line of IoT PLLs

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