"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers."

Hans Bouwmeester
Director of IP
Open-Silicon



When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.


24 Jun 24 True Circuits Introduces the JSPICETM Design Environment (JDETM) at the Design Automation Conference

06 Jul 23 True Circuits Attends 60th Design Automation Conference and Celebrates 25 Years of Timing Excellence!

05 Jul 23 True Circuits Announces Availability of JSPICETM Simulation and Design Environment

08 Jul 22 True Circuits Attends 59th Design Automation Conference

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