"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading design portfolio and flow, our ASIC customers benefit with exceptional performance and reliability. Combined with our custom chip design expertise, these hard macros enable us to quickly and cost-effectively implement ASIC designs with analog components for high-volume applications."

Prasad Subramaniam
Vice President Design Technology
eSilicon



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


20 Jun 18 True Circuits Attends Design Automation Conference

15 May 18 True Circuits Provides Low Power PLL Technology to SiFlower in China

07 May 18 True Circuits Signs Multi-year PLL License with Canaan Creative in China

07 Nov 17 True Circuits Signs Five Year PLL License with Tsinghua University in China

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