"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



With most TCI PLL licenses, integration support is included in the licensing fee. TCI will perform any desired customization for additional fees.


17 Jul 20 True Circuits Participates in First Virtual DAC! Showcases Silicon Proven PLLs, DLLs and DDR 4/3 PHYs

31 May 19 True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at DAC

22 May 19 Response to DeepChip.com article on the demise of analog PLLs, by John Maneatis

20 Jun 18 True Circuits Attends Design Automation Conference

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