"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers."

Hans Bouwmeester
Director of IP
Open-Silicon



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


20 Jun 18 True Circuits Attends Design Automation Conference

15 May 18 True Circuits Provides Low Power PLL Technology to SiFlower in China

07 May 18 True Circuits Signs Multi-year PLL License with Canaan Creative in China

07 Nov 17 True Circuits Signs Five Year PLL License with Tsinghua University in China

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