"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading design portfolio and flow, our ASIC customers benefit with exceptional performance and reliability. Combined with our custom chip design expertise, these hard macros enable us to quickly and cost-effectively implement ASIC designs with analog components for high-volume applications."

Prasad Subramaniam
Vice President Design Technology
eSilicon



When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.


20 Jun 18 True Circuits Attends Design Automation Conference

15 May 18 True Circuits Provides Low Power PLL Technology to SiFlower in China

07 May 18 True Circuits Signs Multi-year PLL License with Canaan Creative in China

07 Nov 17 True Circuits Signs Five Year PLL License with Tsinghua University in China

Copyright © 2002-2018 True Circuits, Inc. All Rights Reserved