"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies



When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.


17 Jul 20 True Circuits Participates in First Virtual DAC! Showcases Silicon Proven PLLs, DLLs and DDR 4/3 PHYs

31 May 19 True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at DAC

22 May 19 Response to DeepChip.com article on the demise of analog PLLs, by John Maneatis

20 Jun 18 True Circuits Attends Design Automation Conference

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