"We chose TCI because of their expertise in PLLs and the proven nature of their PLL designs. By going with TCI in the future, we feel we can spend more time designing our embedded cores and less time doing test chip integration work."

Ken Reimer
Austin Design Center Manager
ARM



A TCI deskew PLL, which provides phase-aligned divide by 1, 2, and 4 clock outputs, can facilitate generating the system clock signals, data strobes, and internal double frequency clocks used to clock the output data. Spread-spectrum PLLs can also be used to generate the system clock to lower EMI emissions.


1 May 18 TSMC NA Technology Symposium
Santa Clara, California

9 May 18 TSMC NA Technology Symposium
Austin, Texas

22 May 18 TSMC China Technology Symposium
Shanghai, China

25-27 Jun 18 Design Automation Conference
San Francisco, California

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