"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading design portfolio and flow, our ASIC customers benefit with exceptional performance and reliability. Combined with our custom chip design expertise, these hard macros enable us to quickly and cost-effectively implement ASIC designs with analog components for high-volume applications."

Prasad Subramaniam
Vice President Design Technology
eSilicon



The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.


17 Jul 20 True Circuits Participates in First Virtual DAC! Showcases Silicon Proven PLLs, DLLs and DDR 4/3 PHYs

31 May 19 True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at DAC

22 May 19 Response to DeepChip.com article on the demise of analog PLLs, by John Maneatis

20 Jun 18 True Circuits Attends Design Automation Conference

Copyright © 2002-2020 True Circuits, Inc. All Rights Reserved