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"We selected TCI's clock generator PLL because of its small size, wide
frequency range and superior low-jitter performance. This will enable our
ASIC customers to successfully implement multiple SPI-4.2 macros in their
high-end telecommunication ASICs and help meet the tight jitter and power
budgets required for 10 Gbps SONET/SDH systems."
Hideya Horikawa
Senior Design Engineering Manager
Renesas
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We provide all of the following for each of our PLLs:
- Complete specifications
- User guidelines
- Behavioral simulation model
- Complete layout (GDSII)
- Layout vs. schematic netlist
- ...
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