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Invites users to attend presentations and Demos at 60th DAC and participate in beta test in advance of full commercial release
LOS ALTOS, California, July 5, 2023 -- True Circuits, Inc.
(TCI), a leading provider of analog and mixed-signal intellectual property
(IP) for the semiconductor, systems and electronics industries announced
today the availability of a beta test for its powerful simulation and
design environment called JSPICETM in advance of a full commercial
release. JSPICE has been under continuous development and use by True
Circuits for over 25 years to create complex analog and digital circuits
and is the basis for the world-class timing and DDR PHY IP that have
made True Circuits an industry leading IP company. JSPICE has allowed
True Circuits to manage every aspect of the definition, design,
characterization, optimization and testing processes in a standardized,
centralized and repeatable way. As a way of giving back to the global
design community, JSPICE is now available for beta testing to a select
group of users in preparation for a full commercial release.
"TCI has long benefited from this powerful environment which allowed
a small design team to simultaneously support a growing family of
mixed-signal IP blocks in over 100 different IC processes from 250nm to
4nm", said John Maneatis, President of True Circuits, Inc. "While
reflecting on the 25th anniversary of
our company and all we have accomplished, what stood out was how
fundamentally important the JSPICE environment has been. It only seemed
fitting that we finally share this incredible enabler with fellow designers
looking for an edge in their ever more challenging work. JSPICE makes
it easy to describe complex circuit structures and rapidly build intuition
with quick and complete characterizations. Once people start using it,
they will never want to work without it."
About JSPICETM
JSPICE is a powerful simulation and design environment that greatly
simplifies and expedites the process of designing and characterizing
complex analog and digital circuits by dramatically facilitating and
enhancing the process of running simulations and interpreting their
results. It provides extended input preprocessing, timing analysis,
mixed-mode simulation, generalized waveform analysis, parametric simulation
sweeps and optimization, parallel simulation job control, network process
and cloud management, and data reduction and output processing.
Characterization flows allow users to encapsulate all information needed
to automatically and fully characterize a design and even generate
reports. JSPICE also provides a powerful mechanism for schematic-based
electrical checks for use by users who want all of the advanced features
of JSPICE, but with a simplified workflow. While JSPICE includes a core
SPICE simulator with some features facilitated by the JSPICE preprocessor,
it can work with any SPICE simulator.
JSPICE makes it easy to express complicated circuits, run a large set
of simulations in parallel, perform complex waveform analysis and reduce
the results to a form easily understandable by the user, all leading to
very rapid turnaround of circuit characterizations. As such, it enables
the user to quickly and easily close the loop on the design process. The
user can iterate through design changes every few minutes after viewing
complete characterization of the circuit rerun after each design change,
allowing users to gain insight into the operation of a circuit in less
than an hour. The short period of time between iterations allows the
user to gain an unprecedented level of insight into the operation of the
circuit so that the design can be completed in a matter of hours rather
than days.
Waveform analysis using JSPICE can be performed on waveform data from
new simulations as well as those that have already been run. The waveform
analysis program is also coupled with a powerful parametric sweep and
optimization engine that is capable of running simulation jobs individually
or in parallel through one of several process servers, including LSF.
The process server included with JSPICE allows users to run single
simulations or thousands in parallel with no additional effort. It enables
the use of local servers as well as seamless and dynamic expansion to
cloud-based servers (AWSTM, AzureTM, Google CloudTM), with the ability to manage millions of
servers and a ridiculously high job processing bandwidth of over 200,000
jobs per second.
For more information about JSPICE, visit
www.truecircuits.com/jspice.html.
JSPICETM at the 60th Design Automation Conference
True Circuits will showcase the JSPICE simulation and design environment
at the 60th Design Automation Conference
(DAC) in San Francisco, CA from July 10 to 12, 2023 at Moscone Convention
Center, West Hall, Booth #1335. DAC attendees will be offered daily
presentations and demos highlighting the features and uses of this
powerful design platform. The JSPICE presentation schedule is as
follows:
Monday July 10, 11:00 AM, 2:00 PM and 4:00 PM
Tuesday July 11, 11:00 AM, 2:00 PM and 4:00 PM
Wednesday July 12, 11:00 AM, 2:00 PM and 4:00 PM
DAC attendees can register for a JSPICE presentation day and time and
also become eligible for a prize at
www.truecircuits.com/jspice_dac2023_pres.html.
For those DAC attendees who would like a private JSPICE demo, please register at
www.truecircuits.com/jspice_dac2023_demo.html.
JSPICETM Beta Test
JSPICE is now available for beta testing to a select group of users
in preparation for a full commercial release. Interested users, whether
individuals, students or employees of companies, can submit a beta test
application at
www.truecircuits.com/jspice_beta.html.
The application process will ask users to agree to the terms of the beta
testing program, including providing periodic feedback and participating
in user forums. Initially a small set of users will be selected by True
Circuits, at its sole discretion, to begin beta testing for a selected
period of time. This set will be expanded later. Approved users will be
provided the JSPICE software suite, user guidelines, related documentation
and a True Circuits point of contact for user support and feedback.
About True Circuits Analog PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven
general purpose, clock generator, deskew, spread spectrum, IoT and Ultra
PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance
points and features typically requested by ASIC, FPGA and SoC designers.
These high quality, low-jitter PLL and DLL hard macros are suited to a
wide variety of interface standards and chip applications. They are
pin-programmable, highly process tolerant and reusable. They are also
easy to integrate and are fully supported, so customers can reduce both
design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication
factors and functions over which they deliver optimal performance,
avoiding the cost and complexity of licensing multiple point-solution
PLLs or fiddling with digital PLLs. TCI's PLLs are available with
ring-oscillator and LC-tank architectures, fractional-N division and
frequency spreading for EMI reduction. TCI's DLLs are available in
multi-slave and multi-phase versions and different sizes and form factors.
They delay a set of signals by precise and adjustable fractions of a
reference clock cycle independent of voltage and temperature and are
ideal for high-speed DDR and ONFI interface applications. Customized PLL
and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer
delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 4nm.
For more information about True Circuits IP products, visit
www.truecircuits.com/tci_technology.html and
www.truecircuits.com/product_matrix.html.
About True Circuits Synthesizable PLLs and DLLs
The synthesizable Precision PLL generates multiple precision clocks
supporting any modulation scheme from almost DC to 10GHz. The outputs
can be independently dynamically programmed cycle-by-cycle to any clock
period and the clock frequency can be a precise ratio of floating point
numbers times the reference frequency. The integrated phase noise is
better than 500ps RMS. It is ideal for SerDes, processor and DVFS
applications.
The synthesizable micro PLL is a small synthesizable general-purpose
PLL that multiplies the reference clock by an integer or fractional-N
value from 1 to 500K. It supports reference clock frequencies as low as
32KHz and output frequencies as high as 3GHz. It can stay locked to the
reference clock while it changes over a 10:1 frequency rang Because it
is synthesizable, it can support spreading as well as other modulation
profiles. It is relatively low power, very fast locking and can quickly
restart from a sleep mode.
The synthesizable micro DLL is a small synthesizable DLL with a master
and multiple slaves topology. It can supp reference frequencies typically
in the range of 500MHz to 3GHz and track reference changes over an 8:1
frequency range while providing 9-bit accuracy in slave delay programming.
Slave delays can be changed glitch free and the DLL can quickly restart
from a sleep mode. It has a very small zero code offset that can be
precisely cancelled.
About True Circuits DDR PHYs
The DDR PHY is a high-performance, scalable system using a radically new
architecture that continuously and automatically adjusts each pin
individually, correcting skew within byte lanes. This state-of-the-art
tuning acts independently on each pin, data phase and chip select value.
Read gate and data eye timing are also continuously adjusted. Fully
automatic training is managed by a light weight special purpose processor
and includes multi-cycle write leveling and read gate training and also
read/write data eye training, including PHY Vref and DRAM Vref settings.
The PHY employs a localized and optimized PHY-to-memory controller
interface to ease timing closure. The circuitry in each pin is able to
measure the data eye and jitter, and calculate flight delays. The PHY
also includes a full speed read/write BIST, which tests the complete
read and write paths of every pin simultaneously with pseudo-random
data.
Remarkable physical flexibility allows the PHY to adapt to each
customer's die floorplan and package constraints, yet is verified and
delivered as a unit for easy timing closure with no assembly required.
The PHY supports LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3, and is DFI 5.1
compliant. When combined with an appropriate DDR memory controller, a
complete and fully-automatic DDR system is realized.
The True Circuits DDR PHY is silicon proven and immediately available
for customer delivery in TSMC's 28/22nm HPC/HPC+ processes. The PHY is
also available upon request in a variety of TSMC processes from 40nm to
4nm. Interested customers can obtain more product information on the
web at
www.truecircuits.com/ddr_phy.html or by contacting True Circuits at sales@truecircuits.com.
About True Circuits
True Circuits develops and markets a broad range of industry leading
PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems
and electronics industries. TCI's robust state-of-the-art circuits,
methodical and proven design strategy, and close association with the
world's leading foundries, IDMs, and design services companies allow the
company to quickly and reliably create new and innovative designs in a
variety of advanced process technologies. Over the last 25 years, True
Circuits has distinguished itself as the technology leader in the timing
IP space, and its PLLs and DLLs are used extensively around the world
in its customers' products with production volumes well into the
billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los
Altos, California 94022 and can be found on the web at www.truecircuits.com.
Product inquiries can be made by calling the company directly at (650)
949-3400 or via e-mail at
sales@truecircuits.com.
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400,
Ext. 3404,
kim@truecircuits.com.
Acronyms and definitions
ASIC Application Specific IC
DLL Delay-Locked Loop
DDR Double Data Rate
FPGA Field Programmable Gate Array
IC Integrated Circuit
IoT Internet of Things
IP Intellectual Property
ONFI Open NAND Flash Interface
PLL Phase-Locked Loop
SoC System on a Chip
"JSPICE" is a trademark of True Circuits, Inc.
"Precision PLL" is a trademark of True Circuits, Inc.
"micro PLL" is a trademark of True Circuits, Inc.
"micro DLL" is a trademark of True Circuits, Inc.
"IoT PLL" is a trademark of True Circuits, Inc.
"Ultra PLL" is a trademark of True Circuits, Inc.
The True Circuits logo is a trademark of True Circuits, Inc.
All other trademarks and tradenames are the property of their respective owners.
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