"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



With most TCI PLL licenses, integration support is included in the licensing fee. TCI will perform any desired customization for additional fees.


27 Jul 26 True Circuits Announces the JSPICETM Design Environment (JDTM) will be Offered to the JDE Ecosystem Open Source

27 Jul 26 Muse and TCI Announce New IP Access ProgramnOffering High-quality PLLs to Universities at Low Cost.
Students and researchers now have easy access to quality IP and MPW services through Muse

27 Jul 26 True Circuits Announces the JSPICETM Design Environment (JDETM) will be Offered Open Source at the Design Automation Conference
Will also Showcase High-performance PLL, DLL and DDR PHY IP

23 Jun 25 True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL that Offers Exceptional Performance, Features and Ease of Use

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