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ULTRA PLL
SPECIFICATION SHEET
PART: TCI-UL65LL-ULHPLL
Version: 1.5
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Divided reference frequency range |
10KHz – 750MHz
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Total output frequency range |
7.32KHz – 3GHz
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/1 output frequency range |
15MHz – 3GHz
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Reference divider values |
1–4096
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Integer feedback divider values |
1–262144 (1–2^18)
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Fractional feedback divider bits (min) |
26 (10 precise)
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Output divider values |
1–2048
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Number of output phases |
2
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Output phase separation |
50% output cycle
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Output phase accuracy |
+/–2.5% output cycle @ 3GHz
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/1 output multiples of div. reference |
1–262144
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Bandwidth adjustment ratio |
1:2^32
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Feedback signal delay (max) |
n/a (FB internal)
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Output duty cycle (nom, tol) |
50%, +/–1%
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Static phase error (max) |
n/a
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Period jitter (P-P) (max) |
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Long-term jitter (RMS) (max) |
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Power dissipation (nom) |
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Reset pulse width (min) |
5us
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Reset /1 output frequency range |
~3GHz if enabled
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Lock time (min allowed) |
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Freq. overshoot (max) |
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Area (including isolation) (max) |
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Number of PLL supply pkg. pins |
1 VDDA, 1 VSSA (preferred)
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Low freq. supply noise est. (P-P) (max) |
10% VDDA
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Low freq. sub. noise est. (P-P) (max) |
10% VDDA
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Ref. input jitter (long-term, P-P) (max) |
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Ref. input spread-spectrum modulation |
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Reference H/L pulse width (min) |
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Synchronous bypass included |
Yes
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Process technology |
UMC L65LL 65nm
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Supply voltage (VDD, VDDA) (nom, tol) |
1.2V, +/–10%
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Junction temperature (nom, min, max) |
70C, –40C, 125C
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