The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.

DESKEW PLL SPECIFICATION SHEET
PART: TCI-UL40G-DSHPLL
Version: 1.5

 

Divided reference frequency range

26.6MHz – 3.4GHz

Total output frequency range

680MHz – 3.4GHz

/1 output frequency range

680MHz – 3.4GHz

Reference divider values

1–64

Feedback divider values

1–64

Divided outputs provided

/1, /2, /4

/1 output multiples of div. reference

1–64

Bandwidth adjustment div. range

1–4096

Feedback signal delay (max)

Output duty cycle (nom, tol)

50%, +/–5% (/1), +/–2% (/N)

/1, /2, /4 rising phase error (max)

Static phase error (max)

Period jitter (P-P) (max)

Input-to-output jitter (P-P) (max)


Power dissipation (nom)

Reset pulse width (min)

5us

Reset /1 output frequency range

340MHz – 1.7GHz

Lock time (min allowed)

/1 freq. overshoot (full-~/half-~) (max)

Area (including isolation) (max)


Number of PLL supply pkg. pins

1 VDDA, 1 VSSA (preferred)

Low freq. supply noise est. (P-P) (max)

10% VDDA

Low freq. sub. noise est. (P-P) (max)

10% VDDA

Ref. input jitter (long-term, P-P) (max)

Reference/Feedback H/L pulse width (min)


Process technology

UMC L40G 40nm

Supply voltage (VDD, VDDA) (nom, tol)

0.9V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

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