The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay line which rejects temperature and supply voltage variations, and has high supply noise rejection for very low jitter operation. TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution.

The analog delay-line architecture used in our DLL design sharply contrasts with those used in digital DLL approaches. The analog control loop allows our DLL to continuously and smoothly compensate its delays to changing voltage and temperature conditions, without any quantization jitter or output glitches. However, digital delay-line control loops, which typically multiplex between inverter outputs along a string of inverters, must select between quantized delay values. Such approaches can lead to imprecise delays and either output glitches from updates or timing drifts from voltage and temperature variations in the absence of updates. The analog delay line used in our DLL design is internally isolated from supply noise for very low output jitter, while digital delay lines tend to be very supply noise sensitive as they convert it percent-for-percent into output jitter. Our analog delay line also provides pulse width compensation to minimize pulse width distortion, unlike digital delay lines. Finally, our DLL design provides very high digital adjustment resolution (typically 7 bits), where the steps are precise fractions of the clock period, unlike digital DLL designs where the adjustment steps are very large and not well calibrated.

DDR DLL SPECIFICATION SHEET
PART: TCI-TN90LP-DDRHDLL
Version: 1.5

 

Reference input frequency range

104MHz – 520MHz

Slave delay adjustment range

0% – 50% of reference cycle

Slave delay adjustment resolution

0.83% of reference cycle

Specified master adjustment setting (MADJ)

120

Allowed master adjustment range (MADJ)

76 – 255

Specified slave adjustment range (ADJ)

0 – 60

Slave delay equation

ADJ[7:0]/MADJ[7:0]·Tref

Number of slaves in cluster

2

Pulse-width distortion (max)

Slave delay DNL (max)

Slave delay INL (max)

Slave delay jitter (P-P) (max)

Total slave timing uncertainty (max)


Power dissipation (nom)

Reset pulse width (min)

1us

Lock time (min allowed)

Area (master + 2 slaves, isolation) (max)


Added core supply package pins

1 VDD and 1 VSS

Low freq. supply noise est. (P-P) (max)

10% VDD

Low freq. sub. noise est. (P-P) (max)

10% VDD

Ref. input jitter (period, P-P) (max)

Reference input duty-cycle range

High/low slave input pulse width (min)

Slave inputs need not be periodic

Reference input 10%-90% edge time (max)

150ps

Slave input 10%-90% edge time (max)

150ps

Slave output loading (max)

200fF


Process technology

TSMC CLN90LP 90nm

Supply voltage (nom, tol)

1.2V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

Copyright © 2002-2016 True Circuits, Inc. All Rights Reserved