The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important.

GENERAL PURPOSE PLL SPECIFICATION SHEET
PART: TCI-TN7FF-GPMPLL
Version: 1.5

 

Divided reference frequency range

15.6MHz – 2GHz

Total output frequency range

25MHz – 2GHz

/1 output frequency range

400MHz – 2GHz

(VCO output internally divided by 2 for 50% DC)

Reference divider values

1–16

Feedback divider values

1–64

Output divider values

1–16

/1 output multiples of div. reference

1–64

Bandwidth adjustment div. range

1–64

Feedback signal delay (max)

Output duty cycle (nom, tol)

50%, +/–2%

Static phase error (max)

Period jitter (P-P) (max)

Input-to-output jitter (P-P) (max)


Power dissipation (nom)

Reset pulse width (min)

5us

Reset /1 output frequency range

200MHz – 1GHz

Lock time (min allowed)

/1 freq. overshoot (full-~/half-~) (max)

Area (including isolation) (max)


Number of PLL supply pkg. pins

1 VDDA, 1 VSSA (preferred)

Low freq. supply noise est. (P-P) (max)

+/–5% VDDA

Low freq. sub. noise est. (P-P) (max)

+/–5% VDDA

Ref. input jitter (long-term, P-P) (max)

Reference/Feedback H/L pulse width (min)


Process technology

TSMC CLN7FF 7nm

Supply voltage (VDD, VDDA) (nom, tol)

0.75V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

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