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MULTI PHASE DLL
SPECIFICATION SHEET
PART: TCI-TN4P-MPHDLL
Version: 1.5
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Reference frequency range |
800MHz – 4GHz
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Output phase delay equation |
D(i) = i/·Tref
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Number of output phases |
16
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Output phase separation |
6.25% output cycle
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Output phase accuracy |
+/–2.5% output cycle @ 4GHz
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Output duty cycle (nom, tol) |
50%, +/–2.5%
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Input-to-output jitter (P-P) (max) |
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Power dissipation (nom) |
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Reset pulse width (min) |
1us
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Lock time (min allowed) |
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Area (max) |
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Added core supply package pins |
1 VDD and 1 VSS
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Low freq. supply noise est. (P-P) (max) |
+/–5% VDD
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Low freq. sub. noise est. (P-P) (max) |
+/–5% VDD
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Ref. input jitter (period, P-P) (max) |
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Reference input duty-cycle range |
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Reference input 10%-90% edge time (max) |
150ps
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Slave output loading (max) |
200fF
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Process technology |
TSMC CLN4P 4nm
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Supply voltage (nom, tol) |
0.75V, +/–10%
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Junction temperature (nom, min, max) |
70C, –40C, 125C
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