The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.

CLOCK GENERATOR PLL SPECIFICATION SHEET
PART: TCI-TN3PLVT-CGHPLL
Version: 1.5

 

Divided reference frequency range

732KHz – 6GHz

Total output frequency range

75MHz – 6GHz

/1 output frequency range

1.2GHz – 6GHz

Reference divider values

1–64

Feedback divider values

1–4096

Output divider values

1, 2–16 (even only)

/1 output multiples of div. reference

1–4096

Bandwidth adjustment div. range

1–4096

Feedback signal delay (max)

n/a (FB internal)

Output duty cycle (nom, tol)

50%, +/–5% (/1), +/–2% (/N)

Static phase error (max)

n/a

Period jitter (P-P) (max)

Input-to-output jitter (P-P) (max)


Power dissipation (nom)

Reset pulse width (min)

5us

Reset /1 output frequency range

600MHz – 3GHz

Lock time (min allowed)

/1 freq. overshoot (full-~/half-~) (max)

Area (including isolation) (max)


Number of PLL supply pkg. pins

1 VDDA, 1 VSSA (preferred)

Low freq. supply noise est. (P-P) (max)

+/–5% VDDA

Low freq. sub. noise est. (P-P) (max)

+/–5% VDDA

Ref. input jitter (long-term, P-P) (max)

Reference H/L pulse width (min)


Process technology

TSMC CLN3P 3nm

Supply voltage (VDD, VDDA) (nom, tol)

0.75V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

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