The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance over a wide frequency range. The analog delay-line architecture used in our DLL design is internally isolated from supply noise for very low output jitter. The analog delay line also provides duty cyle correction.

MULTI PHASE DLL SPECIFICATION SHEET
PART: TCI-TN16FFPGLLVT-MPLDLL
Version: 1.5

 

Reference frequency range

300MHz – 1.5GHz

Output phase delay equation

D(i) = i/·Tref

Number of output phases

16

Output phase separation

6.25% output cycle

Output phase accuracy

+/–2.5% output cycle @ 1.5GHz

Output duty cycle (nom, tol)

50%, +/–2.5%

Input-to-output jitter (P-P) (max)


Power dissipation (nom)

Reset pulse width (min)

1us

Lock time (min allowed)

Area (max)


Added core supply package pins

1 VDD and 1 VSS

Low freq. supply noise est. (P-P) (max)

+/–5% VDD

Low freq. sub. noise est. (P-P) (max)

+/–5% VDD

Ref. input jitter (period, P-P) (max)

Reference input duty-cycle range

Reference input 10%-90% edge time (max)

150ps

Slave output loading (max)

200fF

Process technology

TSMC CLN16FF+GL 16nm

Supply voltage (nom, tol)

0.8V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

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