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CLOCK GENERATOR PLL
SPECIFICATION SHEET
PART: TCI-TN16FFCLLLVT-CGMPLL
Version: 1.5
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Divided reference frequency range |
366KHz – 3GHz
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Total output frequency range |
75MHz – 3GHz
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/1 output frequency range |
600MHz – 3GHz
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(VCO output internally divided by 2 for 50% DC)
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Reference divider values |
1–64
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Integer feedback divider values |
1–4096
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Fractional feedback divider bits |
1
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Output divider values |
1–8
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/1 output multiples of div. reference |
1–4096
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Bandwidth adjustment div. range |
1–4096
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Feedback signal delay (max) |
n/a (FB internal)
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Output duty cycle (nom, tol) |
50%, +/–2%
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Static phase error (max) |
n/a
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Period jitter (P-P) (max) |
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Input-to-output jitter (P-P) (max) |
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Power dissipation (nom) |
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Reset pulse width (min) |
5us
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Reset /1 output frequency range |
300MHz – 1.5GHz
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Lock time (min allowed) |
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/1 freq. overshoot (full-~/half-~) (max) |
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Area (including isolation) (max) |
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Number of PLL supply pkg. pins |
1 VDDA, 1 VSSA (preferred)
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Low freq. supply noise est. (P-P) (max) |
+/–5% VDDA
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Low freq. sub. noise est. (P-P) (max) |
+/–5% VDDA
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Ref. input jitter (long-term, P-P) (max) |
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Reference H/L pulse width (min) |
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Process technology |
TSMC CLN16FFCLL 16nm
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Supply voltage (VDD, VDDA) (nom, tol) |
0.8V, +/–10%
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Junction temperature (nom, min, max) |
70C, –40C, 125C
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