The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable so one PLL can be used for all applications on a SoC. It has ultra-low jitter performance (<500fs) for the most demanding SerDes and ADC reference clocks. It has ultra wide frequency range with multiplication factors over 250,000 to support reference clocks from 32KHz to 1GHz. It has precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. It draws low power in a compact size.

ULTRA PLL SPECIFICATION SHEET
PART: TCI-CL55LPX-ULHPLL
Version: 1.5

 

Divided reference frequency range

10KHz – 812MHz

Total output frequency range

7.32KHz – 3.25GHz

/1 output frequency range

15MHz – 3.25GHz

Reference divider values

1–4096

Integer feedback divider values

1–262144 (1–2^18)

Fractional feedback divider bits (min)

26 (10 precise)

Output divider values

1–2048

Number of output phases

2

Output phase separation

50% output cycle

Output phase accuracy

+/–2.5% output cycle @ 3.25GHz

/1 output multiples of div. reference

1–262144

Bandwidth adjustment ratio

1:2^32

Feedback signal delay (max)

n/a (FB internal)

Output duty cycle (nom, tol)

50%, +/–1%

Static phase error (max)

n/a

Period jitter (P-P) (max)

Long-term jitter (RMS) (max)


Power dissipation (nom)

Reset pulse width (min)

5us

Reset /1 output frequency range

~3.25GHz if enabled

Lock time (min allowed)

Freq. overshoot (max)

Area (including isolation) (max)


Number of PLL supply pkg. pins

1 VDDA, 1 VSSA (preferred)

Low freq. supply noise est. (P-P) (max)

10% VDDA

Low freq. sub. noise est. (P-P) (max)

10% VDDA

Ref. input jitter (long-term, P-P) (max)

Ref. input spread-spectrum modulation

Reference H/L pulse width (min)

Synchronous bypass included

Yes


Process technology

GF L55LPX 55nm

Supply voltage (VDD, VDDA) (nom, tol)

1.2V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

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