The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.

Version: 1.5


Reference frequency range

13.8MHz – 275MHz

Total output frequency range

55MHz – 275MHz

/1 output frequency range

55MHz – 275MHz

(VCO output internally divided by 2 for 50% DC)

Reference divider values


Feedback divider values


Divided outputs provided

/1, /2, /4

/1 output multiples of reference


Feedback signal delay (max)

Output duty cycle (nom, tol)

50%, +/–2%

/1, /2, /4 rising phase error (max)

Static phase error (max)

Period jitter (P-P) (max)

Input-to-output jitter (P-P) (max)

Power dissipation (nom)

Reset pulse width (min)


Reset /1 output frequency range

27.5MHz – 138MHz

Lock time (min allowed)

/1 freq. overshoot (full-~/half-~) (max)

Area (including isolation) (max)

Number of PLL supply pkg. pins

1 VDDA, 1 VSSA (preferred)

Low freq. supply noise est. (P-P) (max)

10% VDDA

Low freq. sub. noise est. (P-P) (max)

10% VDDA

Ref. input jitter (long-term, P-P) (max)

Reference/Feedback H/L pulse width (min)

Process technology

GF L018IC 180nm

Supply voltage (VDD, VDDA) (nom, tol)

1.8V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

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