June 25-27, 2018, Moscone Convention Center, West Hall, Booth #1425
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal
intellectual property (IP) for the semiconductor, systems and electronics
At the Design Automation Conference (DAC), True Circuits will showcase its
complete line of high performance and general purpose PLL and DLL IP, as
well as its innovative and flexible DDR 4/3 PHY. True Circuits is also
celebrating its 20th year in business!
TCI had its humble beginnings in early 1998, with a small but highly
motivated team working out of a conference room at its initial customer.
The challenge in these early days of the IP industry was to convince big
companies they could confidently license analog timing IP from a small
company. TCI quickly realized that it had to devise a family of
standardized timing IP to cover a variety of chip applications, offer
customization to address existing legacy requirements and focus on quality
to make IP integration and testing seamless. With the goal of supporting
many customers, ever changing interface standards and any foundry/IDM
process, TCI took the dramatic decision to develop many of its own CAD tools
to eventually automate all aspects of the design flow.
With the hard work and dedication of many talented employees over the last
20 years, TCI has implemented a highly automated design environment that has
allowed us to easily support many IP design types (PLLs, DLLs, DDR PHYs),
all major foundries and most IDM processes and process variants, and
hundreds of semiconductor customers and design partners from 0.25um to 7nm.
With a global customer base covering a wide spectrum of chip applications
and many billions of chips working in the field, True Circuits is immensely
proud of what we have accomplished and the impact we have had on the
True Circuits has always measured our success by the success of our
customers. Over the past 20 years, we have had the privilege of working on
the most prevalent consumer electronic products and the challenge of meeting
the toughest requirements, but it has always been the learning and the
relationships we have developed with our customers and partners that means
the most to us. Please stop by our booth to say hi and share some memories
from the years gone by. We would be happy to talk about the future as well!
In addition to celebrating 20 years of timing excellence, True Circuits will
discuss a number of topics that should be helpful to chip managers and
designers, including IP selection, IP integration, IP reuse, jitter
specifications and silicon testing.
John Maneatis, Ph.D., True Circuits' President, will make a brief
presentation on how TCI uses automation to take the pain out of IP porting
at the OIP Theater in TSMC's booth #1629 on Monday and Wednesday.
Supporting new process nodes, half nodes and variants can be a challenge for
any design team, but particularly an IP company offering a portfolio of
different designs. To reduce the pain, TCI employs a range of techniques,
from building robust circuits, to using proprietary extensions of CAD tools
to creating designs and deliverables from one, universal database. In his
presentation, John will explain the engineering behind a highly automated
CAD flow that enables TCI to maximize IP consistency, quality and reuse.
John Maneatis and Brian Gardner, True Circuits' V.P. of Business
Development, will also make presentations about True Circuits and our
complete timing IP product portfolio in the ChipEstimate.com booth #2134 on
Monday and Wednesday.
True Circuits will co-host two parties at DAC again this year, including the
HOT Party on the 3rd Floor Mezzanine on Sunday night following the DAC
Welcome Reception, and the Stars of IP Party at the Press Club on Tuesday
night. Come join us and celebrate all that is good with IP!
When and Where
Moscone Convention Center, West Hall, San Francisco, CA
True Circuits Booth #1425
Monday - Wednesday, June 25-27, 10:00 AM to 6:00 PM
TSMC OIP Theater Booth #1629
Title: Automation Takes the Pain out of IP Porting
Presenter: John G. Maneatis, Ph.D.
Monday, June 25, 1:45 PM
Wednesday, June 27, 12:00 PM
ChipEstimate.com Booth #2134
Title: DDR 4/3 Memory Solution
Presenter: Brian Gardner
Monday, June 25, 1:00 PM
Title: 20 Years of Timing Excellence
Presenter: John G. Maneatis, Ph.D.
Wednesday, June 27, 2:00 PM
For more information about True Circuits' PLLs, DLLs and DDR PHYs, please visit
For more information about the Design Automation Conference, please visit
About True Circuits IoT PLLs
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and
running from core power. It has a wide frequency range with multiplication
factors up to 8192, allowing the PLL to run off of a small and inexpensive
32KHz crystal and still clock a 32-bit CPU at up to 250MHz. It is ideal for
IoT applications like wearables and senor devices, where the
power-performance profile must be managed tightly, and possibly over a very
wide frequency range.
About True Circuits Ultra PLLs
The Ultra PLL employs a new state-of-the-art architecture and uses
high-speed digital and analog circuits to achieve exceptional performance,
with many useful features. It has ultra low jitter (<500fs) for the most
demanding SerDes and ADC input clocks. It has ultra wide frequency range
with multiplication factors from 3 to over 250,000, supporting reference
clocks as low as 32KHz. It also has precise frequency control with a least
26 fractional bits (at least 10 precise) for extremely high fractional-N
resolution. It can even generate precise and adjustable frequency spreading
with programmable rate and depth to meet tight FCC requirements. The Ultra
PLL packs all these features into a compact size that draws low power and,
with full pin programmability, one PLL can be used for all applications on a
About True Circuits PLLs and DLLs
In addition to the IoT and Ultra PLLs, True Circuits offers a complete
family of standardized and silicon-proven general purpose, clock generator,
deskew, and spread spectrum PLLs and DDR DLLs that spans nearly all
performance points and features typically requested by ASIC, FPGA and SoC
designers. These high quality, low-jitter PLL and DLL hard macros are
suited to a wide variety of interface standards and chip applications. They
are pin-programmable, highly process tolerant and reusable. They are also
easy to integrate and are fully supported, so customers can reduce both
design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication
factors and functions over which they deliver optimal performance, avoiding
the cost and complexity of licensing multiple point-solution PLLs from
foundries or other vendors. TCI's DLLs are available in mutli-slave and
multi-phase versions and different sizes and form factors. They delay a set
of signals by precise and adjustable fractions of a reference clock cycle
independent of voltage and temperature and are ideal for high-speed DDR and
ONFI interface applications. Customized PLL and DLL solutions are also
available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in
TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 7nm.
For more information about True Circuits timing IP products, visit
About True Circuits DDR PHYs
The DDR 4/3 PHY is a high-performance, scalable system using a radically new
architecture that continuously and automatically adjusts each pin
individually, correcting skew within byte lanes. This state-of-the-art
tuning acts independently on each pin, data phase and chip select value.
Read data eye and gate timing are also continuously adjusted. Automatic
training is included for multi-cycle read gate timing and write leveling,
write data eye timing, and internal and external (on DRAM) Vref setting.
The PHY employs a localized and optimized PHY-to-memory controller interface
to ease timing closure. The circuitry in each pin is able to measure the
data eye and jitter, and calculate flight delays. The PHY also includes a
full speed read/write BIST, which tests the complete read and write paths of
every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's
die floorplan and package constraints, and is delivered and verified as a
single unit for easy timing closure with no assembly required. The PHY is
also DFI 4.0 compliant, and when combined with a suitable DDR 4/3 memory
controller, a complete and fully-automatic DDR 4/3 system is realized.
The True Circuits DDR 4/3 PHY is initially available for customer delivery
in TSMC's 28nm HPC/HPC+ process, with 16nm and 7nm versions to follow.
Interested customers can obtain more product information on the web at
www.truecircuits.com/ddr_phy.html or by
contacting True Circuits at email@example.com.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs,
DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and
electronics industries. TCI's robust state-of-the-art circuits, methodical
and proven design strategy, and close association with the world's leading
foundries, IDMs, and design services companies allow the company to quickly
and reliably create new and innovative designs in a variety of advanced
process technologies. For over 20 years, True Circuits has distinguished
itself as the technology leader in the timing IP space, and its PLLs and
DLLs are used extensively around the world in its customers' products with
production volumes in the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos,
California 94022 and can be found on the web at
www.truecircuits.com. Product inquiries can
be made by calling the company directly at (650) 949-3400 or via e-mail at
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext.
Acronyms and definitions
ASIC Application Specific IC
IC Integrated Circuit
IoT Internet of Things
DLL Delay-Locked Loop
IP Intellectual Property
DDR Double Data Rate
ONFI Open NAND Flash Interface
FPGA Field Programmable Gate Array
PHY Physical Interface
PLL Phase-Locked Loop
SoC System on a Chip
The IoT PLL is a trademark of True Circuits, Inc.
The Ultra PLL is a trademark of True Circuits, Inc. The True Circuits
logo is a trademark of True Circuits, Inc. All other trademarks and
tradenames are the property of their respective owners.