California, April 6, 2015 -- True Circuits, Inc. (TCI), a leading provider
of analog and mixed-signal intellectual property (IP) for the semiconductor,
systems and electronics industries announced today the availability of
a new line of Phase-Locked Loop (PLL) hard macros that is well suited
for the most demanding chip applications, including high-speed SerDes
and ADC input clocks. The "Ultra PLL" is designed as an ultra low jitter,
extremely wide range clock multiplier with precise fractional frequency
control and optional spread spectrum capability, giving chip designers
the ultimate in performance, features and ease of use. It is available
in a variety of TSMC, GLOBALFOUNDRIES and UMC processes.
The Ultra PLL employs a new state-of-the-art architecture and uses
high-speed digital and analog circuits to achieve exceptional performance,
with many useful features. It has ultra low jitter (<500fs) for the most
demanding SerDes and ADC input clocks. It has ultra wide frequency range
with multiplication factors from 3 to over 250,000, supporting reference
clocks as low as 32KHz. It also has precise frequency control with a
least 26 fractional bits (at least 10 precise) for extremely high
fractional-N resolution. It can even generate precise and adjustable
frequency spreading with programmable rate and depth to meet tight FCC
requirements. The Ultra PLL packs all these features into a compact size
that draws low power and, with full pin programmability, one PLL can be
used for all applications on a SoC.
"The growing complexity of today's SoCs and FPGAs presents chip designers
with ever increasing challenges that often result in compromises on
features, performance and flexibility", remarked John Maneatis, Ph.D.,
True Circuits, President. "Our goal is to help chip designers tackle
these challenges with a single PLL that offers broad functionality and
performance in an easy to use programmable hard macro. Whether the need
is ultra low jitter for a SerDes, precise frequency resolution for HDMI
or extremely low phase noise for an ADC, our new state-of-the-art Ultra
PLL has them covered."
Price and Availability
True Circuits Ultra PLLs will be available in TSMC, GLOBALFOUNDRIES and
UMC processes from 65nm to 16nm. Front-end views will be ready for
delivery in the month of May, with tapeout ready GDSII to follow shortly
thereafter. Customers can license TCI timing IP either directly from
TCI or through its global network of design services partners and sales
reps. The hard macros are available for a per use license fee and no
royalty fees. The license fee includes integration support from TCI and
its partners to ensure a successful customer tape out. The deliverables
include GDSII and LVS Spice netlists, behavioral and synthesis models,
Library Exchange Format (LEF) files and extensive user documentation.
About True Circuits PLLs and DLLs
In addition to the new Ultra PLL, True Circuits offers a complete family
of standardized and silicon-proven general purpose, clock generator,
deskew, and spread spectrum PLLs and DDR DLLs that spans nearly all
performance points and features typically requested by ASIC, FPGA and
SoC designers. These high quality, low-jitter PLL and DLL hard macros
are suited to a wide variety of interface standards and chip applications.
They are pin-programmable, highly process tolerant and reusable. They
are also easy to integrate and are fully supported, so customers can
reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication
factors and functions over which they deliver optimal performance,
avoiding the cost and complexity of licensing multiple point-solution
PLLs from foundries or other vendors. TCI's DLLs are available in
mutli-slave and multi-phase versions and different sizes and form factors.
They delay a set of signals by precise and adjustable fractions of a
reference clock cycle independent of voltage and temperature and are
ideal for high-speed DDR and ONFI interface applications. Customized PLL
and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery
in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 16nm. For more
information about True Circuits IP products, visit
About True Circuits DDR PHYs
True Circuits also offers a high performance DDR 4/3 PHY that is a
high-performance, scalable system using a radically new architecture
that continuously and automatically adjusts each pin individually,
correcting skew within byte lanes. This state-of-the-art tuning acts
independently on each pin, data phase and chip select value. Read data
eye and gate timing are also continuously adjusted. Automatic training
is included for multi-cycle read gate timing and write leveling, write
data eye timing, and internal and external (on DRAM) Vref setting.
The PHY employs a localized and optimized PHY-to-memory controller
interface to ease timing closure. The circuitry in each pin is able to
measure the data eye and jitter, and calculate flight delays. The PHY
also includes a full speed read/write BIST, which tests the complete
read and write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's
die floorplan and package constraints, and is delivered and verified as
a single unit for easy timing closure with no assembly required.
The PHY is also DFI 3.1 compliant, and when combined with a suitable DDR
4/3 memory controller, a complete and fully-automatic DDR 4/3 system is
The True Circuits DDR 4/3 PHY is initially available for customer delivery
in TSMC's 28nm HPM/HPC process. The PHY will be available in additional TSMC
and GLOBALFOUNDRIES processes in the very near future. Interested customers
can obtain more product information on the web at
or by contacting True Circuits at firstname.lastname@example.org.
About True Circuits
True Circuits develops and markets a broad range of industry leading
PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems
and electronics industries. TCI's robust state-of-the-art circuits,
methodical and proven design strategy, and close association with the
world's leading foundries, IDMs, and design services companies allow the
company to quickly and reliably create new and innovative designs in a
variety of advanced process technologies. Over the last 17 years, True
Circuits has distinguished itself as the technology leader in the timing
IP space, and its PLLs and DLLs are used extensively around the world
in its customers' products with production volumes in the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los
Altos, California 94022 and can be found on the web at
inquiries can be made by calling the company directly at (650) 949-3400
or via e-mail at email@example.com.
The Ultra PLL is a trademark of True Circuits, Inc. The True Circuits
logo is a trademark of True Circuits, Inc. All other trademarks and
tradenames are the property of their respective owners.