June 2-4, 2014, Moscone Convention Center, Booth #1707
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal
intellectual property (IP) for the semiconductor, systems and electronics
At the Design Automation Conference (DAC), True Circuits will showcase its
new high performance DDR 4/3 PHY with state-of-the-art tuning and training,
and remarkable physical flexibility to adapt to each customer's die
floorplan and package. The DDR 4/3 PHY has been developed using the powerful
custom design automation tools that have made TCI's line of high performance
PLLs and DLLs a staple in the semiconductor industry for over 16 years. The
availability of this revolutionary PHY means customers can now license a
hard PHY with significant performance and features without all the
implementation and timing closure hassles that are common with current DDR
True Circuits will also feature its complete line of standardized and
silicon-proven general purpose, clock generator, deskew, and spread spectrum
PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance
points, features and foundry processes typically requested by ASIC, FPGA and
SoC designers. These high quality, low-jitter PLL and DLL hard macros are
suited to a wide variety of interface standards and chip applications. They
are pin-programmable, highly process tolerant and reusable. Of particular
interest this year is the addition of the TSMC 16nm FF+ and UMC 28nm HPM and
HLP processes to our growing portfolio of timing IP.
True Circuits will discuss these and a number of topics in the True Circuits
booth #1710 that should be helpful to chip managers and designers, including
new standards such as ONFI 4.0, IP selection, IP integration, IP reuse,
jitter specifications and silicon testing.
Stephen Maneatis, True Circuits' CEO, John Maneatis, Ph.D., True Circuits'
President and Brian Gardner, True Circuits' V.P. of Business Development,
will also make presentations about True Circuits and our new DDR PHY IP in
the ChipEstimate.com booth #1533 each day of the conference.
True Circuits will host or co-host a number of parties at DAC again this
year, including a cocktail hour at the ChipEstimate.com booth on Monday
evening, the Heart of Technology (HOT) IP Party at Slims on Monday night and
the Stars of IP Party at Local Edition on Tuesday night. Come join us and
celebrate all that is good about IP!
When and Where
Moscone Convention Center, San Francisco, CA
True Circuits Booth #1707
Monday - Wednesday, June 2-4, 9:00 AM to 6:00 PM
ChipEstimate.com Booth #1533
Monday, June 2, 11:30 AM
Monday, June 2, 5:30 PM (True Circuits hosted cocktail hour)
Tuesday, June 3, 3:00 PM
Wednesday, June 4, 10:30 AM
For more information about True Circuits' PLLs and DLLs, please visit
For more information about the Design Automation Conference, please visit
About True Circuits DDR 4/3 PHY
The True Circuits DDR 4/3 PHY is a high-performance, scalable system using a
radically new architecture that continuously and automatically adjusts each
pin individually, correcting skew within byte lanes. This state-of-the-art
tuning acts independently on each pin, data phase and chip select value.
Read data eye and gate timing are also continuously adjusted. Automatic
training is included for multi-cycle read gate timing and write leveling,
write data eye timing, and internal and external (on DRAM) Vref setting.
The PHY employs a localized, clock deskewed PHY-to-memory controller
interface to ease timing closure. The circuitry in each pin is able to
measure the data eye and jitter, and calculate flight delays. The PHY also
includes a full speed read/write BIST, which tests the complete read and
write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's
die floorplan and package constraints, and is delivered and verified as a
single hard macro for easy timing closure with no assembly required. The PHY
is also DFI 3.1 compliant, and when combined with a suitable DDR 4/3 memory
controller, a complete and fully-automatic DDR 4/3 system is realized.
The True Circuits DDR 4/3 PHY is initially available for customer delivery
in TSMC's 28nm HPM process. The PHY will be available in additional TSMC and
GlobalFoundries processes in the very near future. Interested customers can
obtain more product information on the web at
www.truecircuits.com/ddr_phy.html or by
contacting True Circuits at email@example.com.
About True Circuits PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven
general purpose, clock generator, deskew, and spread spectrum PLLs and DDR
DLLs that spans nearly all performance points and features typically
requested by ASIC, FPGA and SoC designers. These high quality, low-jitter
PLL and DLL hard macros are suited to a wide variety of interface standards
and chip applications. They are pin-programmable, highly process tolerant
and reusable. They are also easy to integrate and are fully supported, so
customers can reduce both design and silicon risks.
True Circuits PLLs are available in a range of frequencies, multiplication
factors (1-4096), sizes and functions over which they deliver optimal
performance, avoiding the cost and complexity of licensing multiple
point-solution PLLs from foundries or other vendors. TCI's DLLs are
available in multi-slave and multi-phase versions and delay a set of signals
by precise and adjustable fractions of a reference clock cycle independent
of voltage and temperature, are ideal for high-speed DDR interface
applications and are available in different sizes and form factors.
Customized PLL and DLL solutions are also available for specialized chip
True Circuits PLLs and DLLs are available for immediate customer delivery in
TSMC, GlobalFoundries, UMC and Common Platform processes from 180nm to 16nm.
For more information about True Circuits timing IP products, visit
About True Circuits
True Circuits develops and markets a broad range of industry leading PLL,
DLL and DDR PHY hard macros for ICs for the semiconductor, systems and
electronics industries. TCI's robust state-of-the-art circuits, methodical
and proven design strategy, and close association with the world's leading
fabs, IDMs, and design services companies allow the company to quickly and
reliably create new and innovative designs in a variety of advanced process
technologies. Over the last 16 years, True Circuits has distinguished
itself as the technology leader in the timing IP space, and its PLLs and
DLLs are used extensively around the world in its customers' products with
production volumes in the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos,
California 94022 and can be found on the web at
www.truecircuits.com. Product inquiries can
be made by calling the company directly at (650) 949-3400 or via e-mail at
Acronyms and definitions
ASIC Application Specific IC
IC Integrated Circuit
DDR Double Data Rate
IP Intellectual Property
DLL Delay-Locked Loop
PLL Phase-Locked Loop
FPGA Field Programmable Gate Array
PHY Physical Interface
SoC System on a Chip
The True Circuits logo is a trademark of True Circuits, Inc. All other
trademarks and tradenames are the property of their respective owners.