"We chose TCI because of their expertise in PLLs and the proven nature of their PLL designs. By going with TCI in the future, we feel we can spend more time designing our embedded cores and less time doing test chip integration work."

Ken Reimer
Austin Design Center Manager
ARM

The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.