"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading design portfolio and flow, our ASIC customers benefit with exceptional performance and reliability. Combined with our custom chip design expertise, these hard macros enable us to quickly and cost-effectively implement ASIC designs with analog components for high-volume applications."

Prasad Subramaniam
Vice President Design Technology
eSilicon


Not usually. All our cell names are prefixed by "TCI_cellname_". As a result, our PLLs do not conflict with each other, and they usually don't conflict with our customers' cell names.


27 Jul 26 True Circuits Announces the JSPICETM Design Environment (JDTM) will be Offered to the JDE Ecosystem Open Source

27 Jul 26 Muse and TCI Announce New IP Access ProgramnOffering High-quality PLLs to Universities at Low Cost.
Students and researchers now have easy access to quality IP and MPW services through Muse

27 Jul 26 True Circuits Announces the JSPICETM Design Environment (JDETM) will be Offered Open Source at the Design Automation Conference
Will also Showcase High-performance PLL, DLL and DDR PHY IP

23 Jun 25 True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL that Offers Exceptional Performance, Features and Ease of Use

Copyright © 2002-2026 True Circuits, Inc. All Rights Reserved